Project · VLSI & AI Chip Design
Design and verify a 5-stage RISC-V core
Build brief for a pipelined RV32I core: RTL, hazard handling, a self-checking testbench, and FPGA synthesis with a timing report.
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The brief
Weeks 1 and 2: single-cycle core passing the RV32I compliance subset. Weeks 3 and 4: pipeline it, add forwarding and stall logic. Weeks 5 and 6: testbench with coverage, synthesise, close timing at the target clock.
What you submit: RTL, testbench, coverage report, synthesis log and a timing summary with your critical path explained.
Rubric weights correctness and the quality of your written analysis equally.