SB
Spandana Bala
ML Engineer
Hyderabad · India
Now at · Infosys
VLSI & AI Chip Design · Practical career preparation
VLSI Physical Design & Static Timing Analysis
Take a digital design from RTL to layout—and explain every timing decision. Learn to constrain, implement and improve a digital block through synthesis, floorplanning, placement, clock-tree synthesis and routing. Use timing and physical reports to diagnose problems and defend a reproducible implementation.
12 core modules
Preparation matched to your diagnostic
Three guided projects integrated into the curriculum
One independently assessed capstone
RoboEdify track record
10,000+
alumni transformed
1,000+
hiring partners
4.8/5
average class rating
87%
placed in 6 months
10+
years of training
Where our AI alumni work
Microsoft
Amazon
Salesforce
ServiceNow
Deloitte
Infosys
Accenture
TCS
Wipro
Capgemini
Cognizant
HCL
MicrosoftAmazonSalesforceServiceNowDeloitteInfosysAccentureTCSWiproCapgeminiCognizantHCL
Direct answer
What does a physical design engineer do?
A physical design engineer turns a digital design into a physical implementation while managing timing, area, connectivity and routing constraints. Static timing analysis checks whether signal paths meet the timing requirements defined for the design. In this course, you work on a supplied verified block and explain the effect of each implementation choice.
The learning journey
01Constrain.
Define clocks, interfaces and the conditions under which the design must operate.
02Implement.
Build a floorplan, place cells, distribute clocks and route the design.
03Analyze.
Read timing and physical reports and investigate the causes of violations.
04Improve.
Compare controlled changes and document the checks behind the final result.
Why this course focuses on practical evidence
A better timing report should come from a better implementation.
You will investigate unconstrained paths, congestion and setup/hold failures. Each improvement must preserve the intended requirements and be checked across the supported scenarios. The goal is to understand why the result changed, not simply to make a report turn green.
Learning format
Learn through classes, labs and individual feedback.
The program combines live mentor-led classes, guided labs, project work and support sessions. Your diagnostic determines the preparation needed before the common core.
Choose on-campus, live online or a working-professional format. An advisor can explain the class format, lab access and learner support before enrollment.
On-campusLive onlineWorking-professional format
Who should join
A common core, with preparation matched to your starting point.
Graduates and learners entering the fieldBuild digital logic, RTL-reading, timing and scripting foundations before entering the common core. You do not need to design a complete processor to begin this pathway.
Working engineersRTL engineers and other experienced learners can demonstrate relevant foundations through the diagnostic. Programming experience alone does not replace digital timing and constraint reasoning.
Learning outcomes
Leave with skills you can demonstrate.
Write meaningful constraintsDefine clocks and IO requirements and explain timing exceptions.
Read implementation inputsUnderstand how libraries, netlists and physical views fit together.
Build and compare floorplansInvestigate utilization, connectivity and routing tradeoffs.
Analyze setup and holdTrace critical paths and explain the effect of clock and data delays.
Improve a physical implementationCompare changes under fixed requirements and supported scenarios.
Defend the handoffPresent reproducible scripts, reports, checks and remaining limitations.
Preparation based on your diagnostic
What you practise before the core.
Linux, Git and Tcl/PythonRun a scripted flow, capture logs, parse timing summaries and reproduce a configuration.
Digital logic and timingTrace sequential paths, reset behavior, skew and clock-to-Q; compute basic setup and hold checks.
RTL and synthesis literacyRead a small datapath, recognize inferred registers/muxes and inspect a synthesized netlist.
CMOS and physical-data foundationsInterpret cell, interconnect, fanout, resistance/capacitance and technology-file concepts.
Both routes complete the same practical exit requirements. A diagnostic identifies the preparation you need. Previously demonstrated foundations can be recognized, while broader gaps receive a separate learning plan before the core.
Course curriculum
12 modules. A complete path from foundations to an independent capstone.
Each module combines technical concepts, practical work, a failure investigation and a reviewed submission. Preparation sits before the common core.
01
Implementation workflow and reproducibility
Physical Design & STA
Make every implementation run traceable.
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01
Implementation workflow and reproducibility
Physical Design & STAMake every implementation run traceable.
Topics
•RTL-to-layout stages
•Input ownership
•Tool/PDK manifests
•Checkpoints
•Report provenance
•Naming and units
Hands-on lab
Reproduce a supplied baseline and locate the input responsible for a deliberate configuration mismatch.
Failure scenario you solve
Two runs use different library revisions, so their timing results cannot be compared fairly.
You build
Flow map, version manifest and run ledger.
Assessed outcome: Rebuild the same checkpoint from a clean workspace.
02
Libraries, netlists and physical databases
Physical Design & STA
Connect timing and physical data to the design.
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02
Libraries, netlists and physical databases
Physical Design & STAConnect timing and physical data to the design.
Topics
•Liberty timing arcs and corners
•LEF/DEF
•Netlist connectivity
•RC data
•Cell footprints
•Technology versus design data
Hands-on lab
Inspect a cell arc and reconcile one net between netlist and physical views; explain a missing-library failure.
Failure scenario you solve
A missing or incompatible cell view prevents the design from linking correctly.
You build
Annotated input inventory and connectivity investigation.
Assessed outcome: Identify incompatible units or missing views before running implementation.
03
SDC and timing foundations
Physical Design & STA
Define the timing requirements before judging the result.
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03
SDC and timing foundations
Physical Design & STADefine the timing requirements before judging the result.
Topics
•Clocks, generated clocks, IO delays, uncertainty, latency, setup/hold, recovery/removal, path groups and unconstrained endpoints
Hands-on lab
Write constraints for an explicitly defined block interface and manually calculate representative paths.
Failure scenario you solve
An interface looks fast only because no IO delay was specified.
You build
Reviewed SDC and path calculations.
Assessed outcome: Detect an unconstrained interface; justify each exception from a functional contract.
04
Synthesis and baseline analysis
Physical Design & STA
Understand what synthesis changed.
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04
Synthesis and baseline analysis
Physical Design & STAUnderstand what synthesis changed.
Topics
•Mapping, optimization tradeoffs, hierarchy, inferred cells, fanout, area and constraint consistency
Hands-on lab
Compare two synthesis configurations with unchanged functional requirements; run regression on any RTL change.
Failure scenario you solve
A smaller netlist misses the target because an optimization lengthened the critical path.
You build
Baseline area/timing report with reproducible configuration.
Assessed outcome: Explain a changed path and distinguish constraint changes from actual design improvement.
05
Floorplanning and power planning
Physical Design & STA
Plan a layout that can be powered and routed.
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05
Floorplanning and power planning
Physical Design & STAPlan a layout that can be powered and routed.
Topics
•Core utilization, aspect ratio, macro placement orientation, halos, channels, IO placement, power connectivity and routability
Hands-on lab
Compare two legal floorplans for a supplied block with a small macro only when the selected platform supports it.
Failure scenario you solve
A tightly packed floorplan leaves insufficient routing space around a macro.
You build
Floorplan rationale and power-connectivity evidence.
Assessed outcome: Predict and explain congestion caused by a poor placement choice.
06
Placement and optimization
Physical Design & STA
Improve placement using matched evidence.
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06
Placement and optimization
Physical Design & STAImprove placement using matched evidence.
Topics
•Global/detailed placement, legalization, congestion, buffering, resizing and density tradeoffs
Hands-on lab
Diagnose a high-fanout or congested region; adjust one variable and compare matched reports.
Failure scenario you solve
Fixing one congested region creates a new timing problem elsewhere.
You build
Before/after report and change log.
Assessed outcome: Improve the stated objective without hiding new violations or changing targets.
07
Clock-tree synthesis
Physical Design & STA
Understand the clock paths behind setup and hold.
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07
Clock-tree synthesis
Physical Design & STAUnderstand the clock paths behind setup and hold.
Topics
•Clock distribution, insertion delay, skew, transition, clock sinks and ideal versus propagated clocks
Hands-on lab
Build a clock tree and trace two sink paths; investigate a hold regression introduced after CTS.
Failure scenario you solve
Timing passes before clock-tree synthesis but develops a hold failure afterward.
You build
Clock-tree review with timing evidence.
Assessed outcome: Explain the impact of skew on both setup and hold for a selected path.
08
Routing and parasitic extraction
Physical Design & STA
Connect routing choices to extracted delay.
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08
Routing and parasitic extraction
Physical Design & STAConnect routing choices to extracted delay.
Topics
•Global/detailed routing, vias, antenna concepts, wire RC, extraction and post-route timing
Hands-on lab
Route the block, review physical violations and compare estimated versus extracted timing.
Failure scenario you solve
A path becomes critical after routing because its wire delay was underestimated.
You build
Routed checkpoint, extraction manifest and violation triage.
Assessed outcome: Locate a physical cause behind a changed critical path.
09
Multi-corner analysis and timing repair
Physical Design & STA
Check a repair across the scenarios that matter.
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09
Multi-corner analysis and timing repair
Physical Design & STACheck a repair across the scenarios that matter.
Topics
•Mode/corner matrices
•Early/late behavior
•Variation concepts
•Setup/hold repair
•False/multicycle paths and constraints audits
Hands-on lab
Analyze all supported declared scenarios and repair one issue while checking for cross-scenario regressions.
Failure scenario you solve
A setup repair in one corner introduces a hold violation in another.
You build
Scenario matrix, exception review and repair evidence.
Assessed outcome: Reject an unjustified false-path fix and explain what supported scenarios do not cover.
10
Physical checks, ECO and handoff
Physical Design & STA
Make the handoff explicit about completed checks.
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10
Physical checks, ECO and handoff
Physical Design & STAMake the handoff explicit about completed checks.
Topics
•DRC/LVS concepts and available decks
•Equivalence after ECO
•Power-integrity introduction
•UPF orientation
•Release manifests
Hands-on lab
Apply a bounded supported ECO and recheck relevant timing/connectivity; classify remaining physical violations.
Failure scenario you solve
A layout file is delivered without evidence that required physical checks ran.
You build
Handoff checklist with executed, unavailable and failed checks separated.
Assessed outcome: Explain why a completed layout is not by itself foundry signoff.
11
Independent implementation capstone
Capstone
Deliver an implementation another engineer can reproduce.
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11
Independent implementation capstone
CapstoneDeliver an implementation another engineer can reproduce.
Topics
•Freeze a block, platform, objective and scenario matrix
•Compare design choices
•Close defined checks
Hands-on lab
Implement the supplied verified block, investigate failures and prepare a defensible release.
Failure scenario you solve
A final result cannot be recreated because the report and configuration came from different runs.
You build
Complete implementation repository and closure report.
Assessed outcome: Reproduce the result and diagnose an unseen timing or configuration defect.
12
Interview and portfolio defense
Career preparation
Explain the design decision behind the tool command.
+
12
Interview and portfolio defense
Career preparationExplain the design decision behind the tool command.
Topics
•Timing-path explanation, constraint review, PPA tradeoffs, report reading and ownership
Hands-on lab
Complete an individual report-reading exercise and technical defense.
Failure scenario you solve
You are asked to justify a timing exception that was copied from another project.
You build
Portfolio case study with source reports.
Assessed outcome: Explain decisions without relying on memorized commands.
Scope note: Core depth is block implementation and timing reasoning. Full-chip power planning, advanced-node signoff, detailed SI/EM/IR closure, UPF implementation and tapeout are introductions or later specializations. RTL authorship is the responsibility of the RTL course; UVM environment development belongs to verification.
Tools and methods
Use a focused stack to build and explain your work.
Tcl, Python, Linux and GitAutomate runs and keep inputs and results reproducible.
OpenROAD-based flowPractise physical implementation on a qualified platform.
OpenSTA and timing reportsAnalyze constrained paths and supported timing scenarios.
Liberty, LEF/DEF and netlistsUnderstand timing, connectivity and physical data.
Physical viewers and available check decksInspect the implementation and report the checks actually run.
The core uses a qualified open physical-design flow and compatible platform. Any commercial-tool extension will be described separately. The lab setup and computer or server access requirements are explained before enrollment.
Projects and portfolio
Three guided projects, followed by an independent capstone.
The guided projects develop across the modules and are part of the core curriculum.
Guided project 1
Constraint and timing audit
Build an SDC file for a supplied block, calculate representative paths and identify missing or unjustified constraints.
Portfolio evidence
Reviewed SDCPath calculationsConstraint audit
Guided project 2
Floorplan and placement comparison
Compare two implementation choices using the same design and target. Investigate congestion, area and timing changes.
Portfolio evidence
Floorplan snapshotsMatched reportsChange log
Guided project 3
Post-route timing investigation
Inspect a clock tree, extracted timing and a bounded timing repair. Check whether the repair introduces a new issue elsewhere.
Portfolio evidence
Clock-path reviewViolation analysisRepair evidence
Capstone
Reproducible physical implementation of a digital block
Take a supplied packet-buffer/control block through the qualified physical flow. Freeze the platform and constraints, compare two implementation choices and explain the checks supporting your final result.
What you submit
- •A clear scope, design or integration plan, and acceptance checklist.
- •Your source files, scripts and configuration with a readable project guide.
- •Implementation scripts, constraint reviews, timing investigations and physical reports.
- •A failure investigation showing the cause, correction and recheck.
- •A final report explaining results, assumptions and remaining limitations.
- •An individual walkthrough and an unfamiliar debugging task.
What the assessor checks: Your implementation addresses the agreed project requirements, tests the relevant boundary and failure cases, and can be reproduced from the submitted materials. You explain your own contribution and support conclusions with actual results. A polished group demonstration alone does not meet the individual exit requirement.
Assessment and completion
Demonstrate what you can do.
RoboEdify · Certificate of Completion
VLSI Physical Design & Static Timing Analysis
Presented to
Learner name
Awarded for completing the course's practical assessments and independently defending its capstone project.
Manikanta Kona
Founder · RoboEdify
ROBO
EDIFY
CERT
EDIFY
CERT
30%
Module labs
20%
Practical checkpoints
35%
Capstone
15%
Individual debugging and defense
The proposed completion standard is 70% overall, at least 60% separately in the capstone and individual defense, and completion of all mandatory practical requirements. Feedback identifies specific gaps for remediation and reassessment.
This is a proposed RoboEdify course credential. External accreditation, vendor certification and partner endorsement are not implied by the course title.
Career preparation
Prepare for relevant roles with work you can explain.
Physical Design TraineePractise block implementation and report-driven debugging.
Junior Implementation EngineerDevelop skills in constraints, placement, routing and controlled optimization.
STA TraineeBuild timing-path reasoning and constraint-review experience.
Your career-preparation work includes a reviewed technical project summary, a readable repository, resume statements grounded in your contribution and a live technical interview. Role eligibility depends on each employer's requirements and your demonstrated skills.
Career support
Build your portfolio. Prepare your profile. Practise your interviews.
Career support includes portfolio and profile preparation, interview practice, and role-fit introductions where available. The shared hiring-partner network includes Infosys, TCS, Deloitte, Accenture, Cognizant, NTT Data and Capgemini.
01 / PORTFOLIO
Evidence from your own work.
For this course, your portfolio centres on implementation scripts, constraint reviews, timing investigations and physical reports you complete.
02 / PROFILE
Profile and resume preparation.
A reviewed technical project summary, a readable repository and resume statements grounded in your contribution.
03 / INTERVIEWS
Interview practice and introductions.
Technical interview practice, with role-fit introductions where available.
RoboEdify does not guarantee an interview, offer, salary, employer, location or timeline.
Institute leadership
Meet the team behind RoboEdify.
MK
Manikanta Kona
Founder, RoboEdify · Enterprise AI Architect
Enterprise AI · Agentic Systems · LLM Platforms · Robotics & Edge AI
15 yrs
ENTERPRISE AI
2,400+
LEARNERS
4.9 /5
RATING
Manikanta brings 15 years of enterprise platform architecture experience from AT&T, Salesforce, Cox Communications and Broadcom. His background includes enterprise platform and AI rollouts for Fortune-500 banks, telcos and insurers, and production agentic-AI deployments for governed case handling.
Education: M.S. in Engineering, Purdue University.
RK
Ravi Krishna
Chief Technologist, RoboEdify · Implementation & Delivery Lead
Enterprise automation · Deployment · Evaluation evidence · Delivery governance
10 yrs
IMPLEMENTATION & DELIVERY
1,800+
LEARNERS
4.8 /5
RATING
Ravi leads RoboEdify's implementation and delivery practice. His background spans enterprise automation programs, deployment, evaluation evidence and delivery governance.
Industry voices from RoboEdify’s AI programs
What employers say about RoboEdify’s AI and robotics graduates.
The following testimonials retain their original program context. They describe AI, robotics and enterprise-program experience, rather than outcomes from this course.
RoboEdify grads ramp 40% faster on applied AI projects than typical hires. Best AI engineering pipeline in India.
Aakash Mehta, Partner Programme Lead, Microsoft
We've onboarded 80+ RoboEdify alumni in 18 months. Lowest ramp time we've seen for ML plus AI agent practices.
Anita Sharma, Senior Manager, Deloitte
The programme is comprehensive — predictive ML, LLM systems, plus agentic and robotics work. Grads come pre-trained for enterprise.
Rahul Bhatt, Solutions Lead, Mphasis
Their agent + robotics track produces engineers who ship production-grade perception and control code on day one. Genuinely rare.
Deepak Pillai, Senior Architect, TCS
What sets RoboEdify apart is the simulation-to-hardware layer baked into the AI track. Our clients ask for exactly this profile.
Suresh Menon, Practice Lead, Accenture
Their fundamentals prep is rigorous, and the capstone with a real deployed system and safety case is what closes interviews for us.
Vikram Iyer, Director, Infosys
RoboEdify's AI grads get models into production twice as fast in the first 90 days. Our internal metrics back this up clearly.
Lakshmi Nair, VP Engineering, Wipro
Best AI + robotics pipeline we've sourced from in India. Their projects are production work, not toy code.
Karthik Subramanian, Engineering Director, Cognizant
Strong ML and edge-deployment foundation. Their grads need almost zero ramp time on enterprise engagements with us.
Arun Joshi, Practice Director, Capgemini
We've placed 40+ RoboEdify alumni across our AI and automation teams. Strong fundamentals, sharp on the agent stack.
Sanjay Verma, Talent Director, IBM
ITOM + Predictive Intelligence is exactly the talent gap we've been struggling to close. RoboEdify is filling it for us reliably.
Anjali Desai, Practice Head, LTIMindtree
Their AI track delivers engineers who navigate data, models and integrations on customer engagements unsupervised.
Ramesh Iyer, Senior Manager, Tech Mahindra
Hired 25+ RoboEdify graduates for our AI practice. Strong coding, strong ML depth, sharp on the agent layer.
Geetha Pillai, Talent Acquisition Lead, Cyient
RoboEdify grads who blend robotics with Azure OpenAI land production-ready on day one. Rare combination, well-trained.
Priya Reddy, Talent Lead, Microsoft
AI alumni across RoboEdify
Meet alumni featured in our AI programs.
NV
Naveen Vedala
AI Agent Engineer
Hyderabad · India
Now at · TCS
TA
Tejashwini Addla
Simulation Engineer
Hyderabad · India
Now at · Deloitte
TD
Tharunesh Dillikar
Robotics Software Engineer
Seattle · United States
Now at · Accenture
MM
Mujahed Mohammed
Edge AI Engineer
Hyderabad · India
Now at · Accenture
BK
Bhargav Kumar Murala
Physical AI Engineer
Hyderabad · India
Now at · Capgemini
SL
Sai Manasa Leburi
Autonomous Systems Engineer
New York · United States
Now at · NTT Data
RD
Rahul Dhamma
Robot Learning Engineer
Hyderabad · India
Now at · Cognizant
Our locations
Come chat with us—on campus or online.
Flagship campus
Hyderabad
2nd Floor, Hitech City Road · Above Domino's · Opp. Cyber Towers, Jai Hind Enclave ·
Hyderabad, Telangana
Call
+91 8142998866
US desk
+1 256 388 7766
Opening hours
Mon–Sun · 7 AM–9 PM
Online
Global
Live online classes and mentorship, with working-professional learning options. Physical-design labs use a qualified implementation platform and timing-analysis environment.
Format
Live online + mentorship
Options
Working-professional
Learning support
Support when you need to catch up.
Freeze your seat for up to 90 days and rejoin the next class at no extra fee. TAs run catch-up sessions every Saturday, and recordings of every live session are available for the lifetime of your account.
FAQs
Questions about prerequisites, tools and completion.
Do I need prior physical-design experience?
No. You need digital logic, RTL-reading and timing foundations, which are checked through the diagnostic and supported by preparation.
Will I write the RTL for the final project?
The core project starts from supplied verified RTL so you can focus on implementation and timing. RTL authorship is covered in the separate RTL course.
Will I learn commercial EDA tools?
The common labs use a qualified open flow. Commercial-tool exposure depends on the specifically offered extension and its licence access; it is not implied by the base syllabus.
Does the course include tapeout?
The capstone is a teaching implementation with documented checks. It does not by itself establish foundry signoff or tapeout readiness.
Do I need an FPGA board?
No. The core focuses on physical implementation and timing analysis using the selected software environment.
Can graduates and working engineers both join?
Yes, subject to the stated entry requirements. Both follow the same practical core, with preparation assigned through a diagnostic. Advanced pathways require the relevant foundations before their bridge.
How is the learning workload structured?
The program combines live mentor-led classes, guided labs, project work and support sessions. An advisor can explain the current class format before enrollment.
Can I study online or on campus?
RoboEdify offers its Hyderabad campus, live online classes and a working-professional format. Discuss the course-specific lab access and class format with an advisor.
What if I fall behind or need to pause?
You can freeze your seat for up to 90 days and rejoin the next class at no extra fee. Saturday catch-up sessions and recordings of every live session support your learning. Recordings remain available for the lifetime of your account.
Is placement guaranteed?
No. Career support includes portfolio and profile preparation, interview practice and role-fit introductions where available. RoboEdify does not guarantee an interview, offer, salary, employer, location or timeline.
What if I do not meet a practical requirement?
Feedback identifies the missing capability and the work needed for reassessment. Attendance alone does not meet the proposed completion standard. Confirm course-specific reassessment arrangements before enrollment.
How can I learn about fees and lab access?
Speak to a course advisor about the current offering, preparation requirements, fees, equipment or software access and learner-support terms.
Still have a question?
Find your starting point in Physical Design & STA.
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Plan your learning
- Course
- VLSI Physical Design & Static Timing Analysis
- Preparation
- Diagnostic-based preparation before the common core
- Level
- Specialist
- Curriculum
- 12 modules
Confirm your intake dates, delivery mode, fees, assessment and practical access with RoboEdify before enrolling. Course content describes the learning scope; an enquiry does not reserve a seat.