SB
Spandana Bala
ML Engineer
Hyderabad · India
Now at · Infosys
VLSI & AI Chip Design · Practical career preparation
Design for Testability Scan, ATPG & MBIST
Make hardware testable—and show which faults your tests detect. Learn scan architecture, pattern generation, fault analysis and memory-test fundamentals through practical design-for-test exercises. Build a test flow, investigate missed faults and explain the evidence behind your coverage report.
11 core modules
Preparation matched to your diagnostic
Three guided projects integrated into the curriculum
One independently assessed capstone
RoboEdify track record
10,000+
alumni transformed
1,000+
hiring partners
4.8/5
average class rating
87%
placed in 6 months
10+
years of training
Where our AI alumni work
Microsoft
Amazon
Salesforce
ServiceNow
Deloitte
Infosys
Accenture
TCS
Wipro
Capgemini
Cognizant
HCL
MicrosoftAmazonSalesforceServiceNowDeloitteInfosysAccentureTCSWiproCapgeminiCognizantHCL
Direct answer
What does a DFT engineer do?
A design-for-test engineer adds and validates structures that make a chip easier to test for manufacturing defects. The work includes scan chains, test-mode controls, pattern generation and analysis of fault-model coverage. This course develops those skills on small digital blocks and a bounded memory-test model.
The learning journey
01Plan.
Map test modes, clocks, resets and access.
02Insert.
Build and validate scan structures.
03Generate.
Create patterns and evaluate what they detect.
04Diagnose.
Investigate coverage gaps and memory-test failures.
Why this course focuses on practical evidence
A coverage number needs a fault model and an explanation.
You will inspect scan failures, uncontrolled resets, masked values and undetected faults. Each exercise connects the test procedure to the fault it is meant to reveal, so you can explain both detection and limitations.
Learning format
Learn through classes, labs and individual feedback.
The program combines live mentor-led classes, guided labs, project work and support sessions. Your diagnostic determines the preparation needed before the common core.
Choose on-campus, live online or a working-professional format. An advisor can explain the class format, lab access and learner support before enrollment.
On-campusLive onlineWorking-professional format
Who should join
A common core, with preparation matched to your starting point.
Graduates and learners entering the fieldPrepare through digital logic, RTL/netlist reading, simulation and scripting. Prior DFT-tool experience is not required.
Working engineersEngineers with relevant digital-design experience can demonstrate readiness through the diagnostic. All learners complete the same scan, pattern-analysis and fault-reasoning assessments.
Learning outcomes
Leave with skills you can demonstrate.
Plan a test architectureDefine test access, modes and clock/reset controls.
Validate scan chainsDemonstrate shift/capture behavior and normal-mode operation.
Generate and inspect patternsUse the qualified ATPG flow and independently inspect selected results.
Explain fault coverageReport detections, exclusions and tool classifications accurately.
Build a teaching MBIST controllerTrace a memory-test algorithm and demonstrate detection of declared faults.
Diagnose test failuresSeparate design, pattern, simulation and setup causes.
Preparation based on your diagnostic
What you practise before the core.
Linux, Git and scriptingRun batch jobs and summarize fault/pattern reports.
Digital logic and sequential timingExplain controllability, observability, clocking and reset.
RTL, simulation and netlistsTrace a state machine and validate a small design with a self-checking testbench.
Test reasoning foundationsPropagate a stuck-at fault and distinguish a functional mismatch from a test-mode setup error.
Both routes complete the same practical exit requirements. A diagnostic identifies the preparation you need. Previously demonstrated foundations can be recognized, while broader gaps receive a separate learning plan before the core.
Course curriculum
11 modules. A complete path from foundations to an independent capstone.
Each module combines technical concepts, practical work, a failure investigation and a reviewed submission. Preparation sits before the common core.
01
Manufacturing test and fault models
DFT: Scan, ATPG & MBIST
Connect a logical fault model to observable failures.
+
01
Manufacturing test and fault models
DFT: Scan, ATPG & MBISTConnect a logical fault model to observable failures.
Topics
•Defects versus logical fault models
•Controllability/observability
•Stuck-at and transition models
•Fault simulation
•Test escapes
Hands-on lab
Enumerate faults in a small circuit and calculate detections by hand before comparing a tool report.
Failure scenario you solve
A high model-coverage result is mistakenly presented as proof that every physical defect will be detected.
You build
Fault table and test strategy.
Assessed outcome: Explain why model coverage does not equal defect coverage or yield.
02
Test architecture and planning
DFT: Scan, ATPG & MBIST
Make every test control deliberate.
+
02
Test architecture and planning
DFT: Scan, ATPG & MBISTMake every test control deliberate.
Topics
•Test modes, reset control, clock controllability, hierarchy, test ports, access and functional isolation
Hands-on lab
Draw a block-level test architecture and trace every test control through shift and capture.
Failure scenario you solve
A reset cannot be controlled in test mode, preventing the intended capture.
You build
DFT plan and mode table.
Assessed outcome: Find an uncontrollable clock/reset or a conflicting mode assumption.
03
Scan insertion and chain validation
DFT: Scan, ATPG & MBIST
Prove the scan chain moves the expected bits.
+
03
Scan insertion and chain validation
DFT: Scan, ATPG & MBISTProve the scan chain moves the expected bits.
Topics
•Scan cells, stitching, chain length, scan enable, lockup-latch purpose, clock-domain grouping and test-rule checks
Hands-on lab
Insert scan using the qualified flow; simulate shift/capture and debug a broken chain.
Failure scenario you solve
A reversed connection corrupts the shifted pattern before capture.
You build
Insertion script, chain report and simulation traces.
Assessed outcome: Show correct serial transport and preserved functional behavior in normal mode.
04
ATPG and pattern simulation
DFT: Scan, ATPG & MBIST
Trace why a pattern detects—or misses—a fault.
+
04
ATPG and pattern simulation
DFT: Scan, ATPG & MBISTTrace why a pattern detects—or misses—a fault.
Topics
•Activation, propagation, justification, pattern generation, simulation, masking, tool constraints and fault classifications
Hands-on lab
Generate stuck-at patterns, simulate selected patterns and trace one detected and one undetected fault.
Failure scenario you solve
A fault remains undetected because a constraint prevents its effect from reaching an observation point.
You build
Pattern set and fault-classification report.
Assessed outcome: Explain coverage numerator/denominator and verify a pattern independently.
05
At-speed test foundations
DFT: Scan, ATPG & MBIST
Separate shift correctness from capture timing.
+
05
At-speed test foundations
DFT: Scan, ATPG & MBISTSeparate shift correctness from capture timing.
Topics
•Launch/capture timing
•Transition tests
•Launch-on-capture/shift concepts
•Clock-controller role and timing constraints
Hands-on lab
Generate and validate bounded transition patterns where the licensed flow supports them; inspect a capture failure.
Failure scenario you solve
Scan shifting works, but the capture procedure uses the wrong clock behavior.
You build
At-speed test procedure and timing assumptions.
Assessed outcome: Distinguish a scan shift defect from a capture timing or test-procedure issue.
06
Coverage improvement and compression
DFT: Scan, ATPG & MBIST
Improve detection without hiding the problem.
+
06
Coverage improvement and compression
DFT: Scan, ATPG & MBISTImprove detection without hiding the problem.
Topics
•Untestable versus aborted faults
•X sources
•Test points
•Compression architecture, aliasing concepts and power limits
Hands-on lab
Classify coverage holes; evaluate a permitted test-point or constraint change. Compression lab uses the selected licensed feature or an explicitly labelled teaching model.
Failure scenario you solve
An X mask raises the apparent coverage while concealing useful observations.
You build
Before/after fault report and change justification.
Assessed outcome: Improve coverage without masking a functional node merely to raise a percentage.
07
MBIST and memory fault models
DFT: Scan, ATPG & MBIST
Test memory behavior against a declared model.
+
07
MBIST and memory fault models
DFT: Scan, ATPG & MBISTTest memory behavior against a declared model.
Topics
•Memory interface contract
•March-style algorithms
•Address/data sequencing
•Stuck-at, transition and selected coupling models
•Repair concepts
Hands-on lab
Implement a small teaching MBIST controller and inject specified faults into a behavioral memory model.
Failure scenario you solve
The controller skips an address and misses a fault at that location.
You build
Controller RTL, algorithm trace and detection matrix.
Assessed outcome: Show correct failure address/data and explain faults outside the chosen algorithm/model.
08
JTAG and test access
DFT: Scan, ATPG & MBIST
Navigate a bounded test-access path.
+
08
JTAG and test access
DFT: Scan, ATPG & MBISTNavigate a bounded test-access path.
Topics
•TAP state-machine concepts
•Instruction/data paths
•Boundary scan purpose
•Internal test-access orientation
Hands-on lab
Simulate a bounded TAP teaching model and read/write a selected test register.
Failure scenario you solve
An incorrect TAP transition updates the wrong register.
You build
TAP trace and access procedure.
Assessed outcome: Navigate reset and shift/update sequences and explain the model scope.
09
Integration, patterns and diagnosis
DFT: Scan, ATPG & MBIST
Reduce a test failure to a clear cause.
+
09
Integration, patterns and diagnosis
DFT: Scan, ATPG & MBISTReduce a test failure to a clear cause.
Topics
•Functional/test constraints, scan reorder awareness, pattern export, chain failures, test time and tester handoff terminology
Hands-on lab
Investigate an injected integration failure and reproduce it from a minimal pattern.
Failure scenario you solve
A simulation mismatch is blamed on the design when the test procedure is inconsistent.
You build
Integration checklist and diagnostic report.
Assessed outcome: Separate design, pattern, simulation and test-setup causes with evidence.
10
Independent DFT capstone
Capstone
Deliver patterns and a defensible fault report.
+
10
Independent DFT capstone
CapstoneDeliver patterns and a defensible fault report.
Topics
•Small scan-enabled control/datapath block plus teaching MBIST memory
•Reproducible test flow and closure
Hands-on lab
Complete scan/ATPG validation, memory fault injection and a fault-coverage review.
Failure scenario you solve
The reported coverage cannot be reproduced from the archived constraints and patterns.
You build
DFT handoff package and individual defense.
Assessed outcome: Reproduce patterns and detect assessor-selected reachable defects.
11
Interview and portfolio defense
Career preparation
Explain testability from first principles.
+
11
Interview and portfolio defense
Career preparationExplain testability from first principles.
Topics
•Scan timing, fault reasoning, report interpretation and practical debugging
Hands-on lab
Explain one undetected fault and debug an unseen scan-mode problem.
Failure scenario you solve
An assessor asks why a specific fault is untestable, not which command generated the report.
You build
Portfolio case study and corrected test procedure.
Assessed outcome: Demonstrate independent fault reasoning rather than tool-command recall.
Scope note: Core depth is scan, bounded ATPG and memory-test reasoning. Compression implementation depends on licensed capability. Production repair flows, advanced fault models, silicon diagnosis, IJTAG implementation and production ATE programming are orientation topics. Do not imply that a behavioral MBIST model validates a physical SRAM.
Tools and methods
Use a focused stack to build and explain your work.
Qualified scan/ATPG flowInsert and validate scan structures and generate patterns.
RTL and gate-level simulationCheck functional mode, shift/capture and selected patterns.
Tcl/Python, Linux and GitAutomate runs and track constraints and results.
Behavioral memory and fault modelsEvaluate a bounded MBIST controller.
Waveform and report toolsInvestigate test-mode and detection failures.
The practical scan/ATPG track requires the selected licensed flow and compatible simulation. The exact tools and access arrangements will be specified before enrollment. A foundations-only offering without that access would have a different scope.
Projects and portfolio
Three guided projects, followed by an independent capstone.
The guided projects develop across the modules and are part of the core curriculum.
Guided project 1
Scan architecture and chain validation
Plan test controls, insert scan in the qualified flow and diagnose an intentionally broken chain.
Portfolio evidence
Mode tableInsertion scriptsShift/capture traces
Guided project 2
ATPG coverage investigation
Generate patterns for a small circuit, inspect detected and undetected faults and validate selected patterns in simulation.
Portfolio evidence
Pattern manifestFault reportSimulation evidence
Guided project 3
Memory-test controller
Implement a small March-style teaching controller and inject specified faults into a behavioral memory.
Portfolio evidence
Controller RTLAlgorithm traceDetection matrix
Capstone
Scan, ATPG and memory-test validation package
Deliver a reproducible test flow for a supplied controller/datapath, together with a separate teaching MBIST demonstration. Explain chain operation, generated patterns, coverage gaps and the limits of the fault models used.
What you submit
- •A clear scope, design or integration plan, and acceptance checklist.
- •Your source files, scripts and configuration with a readable project guide.
- •Scan procedures, pattern simulations, fault reports and memory-test evidence.
- •A failure investigation showing the cause, correction and recheck.
- •A final report explaining results, assumptions and remaining limitations.
- •An individual walkthrough and an unfamiliar debugging task.
What the assessor checks: Your implementation addresses the agreed project requirements, tests the relevant boundary and failure cases, and can be reproduced from the submitted materials. You explain your own contribution and support conclusions with actual results. A polished group demonstration alone does not meet the individual exit requirement.
Assessment and completion
Demonstrate what you can do.
RoboEdify · Certificate of Completion
Design for Testability: Scan, ATPG & MBIST
Presented to
Learner name
Awarded for completing the course's practical assessments and independently defending its capstone project.
Manikanta Kona
Founder · RoboEdify
ROBO
EDIFY
CERT
EDIFY
CERT
30%
Module labs
20%
Practical checkpoints
35%
Capstone
15%
Individual debugging and defense
The proposed completion standard is 70% overall, at least 60% separately in the capstone and individual defense, and completion of all mandatory practical requirements. Feedback identifies specific gaps for remediation and reassessment.
This is a proposed RoboEdify course credential. External accreditation, vendor certification and partner endorsement are not implied by the course title.
Career preparation
Prepare for relevant roles with work you can explain.
DFT TraineePractise test-mode planning and scan validation.
Junior Scan/ATPG EngineerDevelop pattern-generation and coverage-investigation skills.
Test-Engineering TraineeBuild fault-model reasoning and reproducible test reporting.
Your career-preparation work includes a reviewed technical project summary, a readable repository, resume statements grounded in your contribution and a live technical interview. Role eligibility depends on each employer's requirements and your demonstrated skills.
Career support
Build your portfolio. Prepare your profile. Practise your interviews.
Career support includes portfolio and profile preparation, interview practice, and role-fit introductions where available. The shared hiring-partner network includes Infosys, TCS, Deloitte, Accenture, Cognizant, NTT Data and Capgemini.
01 / PORTFOLIO
Evidence from your own work.
For this course, your portfolio centres on scan procedures, pattern simulations, fault reports and memory-test evidence you complete.
02 / PROFILE
Profile and resume preparation.
A reviewed technical project summary, a readable repository and resume statements grounded in your contribution.
03 / INTERVIEWS
Interview practice and introductions.
Technical interview practice, with role-fit introductions where available.
RoboEdify does not guarantee an interview, offer, salary, employer, location or timeline.
Institute leadership
Meet the team behind RoboEdify.
MK
Manikanta Kona
Founder, RoboEdify · Enterprise AI Architect
Enterprise AI · Agentic Systems · LLM Platforms · Robotics & Edge AI
15 yrs
ENTERPRISE AI
2,400+
LEARNERS
4.9 /5
RATING
Manikanta brings 15 years of enterprise platform architecture experience from AT&T, Salesforce, Cox Communications and Broadcom. His background includes enterprise platform and AI rollouts for Fortune-500 banks, telcos and insurers, and production agentic-AI deployments for governed case handling.
Education: M.S. in Engineering, Purdue University.
RK
Ravi Krishna
Chief Technologist, RoboEdify · Implementation & Delivery Lead
Enterprise automation · Deployment · Evaluation evidence · Delivery governance
10 yrs
IMPLEMENTATION & DELIVERY
1,800+
LEARNERS
4.8 /5
RATING
Ravi leads RoboEdify's implementation and delivery practice. His background spans enterprise automation programs, deployment, evaluation evidence and delivery governance.
Industry voices from RoboEdify’s AI programs
What employers say about RoboEdify’s AI and robotics graduates.
The following testimonials retain their original program context. They describe AI, robotics and enterprise-program experience, rather than outcomes from this course.
RoboEdify grads ramp 40% faster on applied AI projects than typical hires. Best AI engineering pipeline in India.
Aakash Mehta, Partner Programme Lead, Microsoft
We've onboarded 80+ RoboEdify alumni in 18 months. Lowest ramp time we've seen for ML plus AI agent practices.
Anita Sharma, Senior Manager, Deloitte
The programme is comprehensive — predictive ML, LLM systems, plus agentic and robotics work. Grads come pre-trained for enterprise.
Rahul Bhatt, Solutions Lead, Mphasis
Their agent + robotics track produces engineers who ship production-grade perception and control code on day one. Genuinely rare.
Deepak Pillai, Senior Architect, TCS
What sets RoboEdify apart is the simulation-to-hardware layer baked into the AI track. Our clients ask for exactly this profile.
Suresh Menon, Practice Lead, Accenture
Their fundamentals prep is rigorous, and the capstone with a real deployed system and safety case is what closes interviews for us.
Vikram Iyer, Director, Infosys
RoboEdify's AI grads get models into production twice as fast in the first 90 days. Our internal metrics back this up clearly.
Lakshmi Nair, VP Engineering, Wipro
Best AI + robotics pipeline we've sourced from in India. Their projects are production work, not toy code.
Karthik Subramanian, Engineering Director, Cognizant
Strong ML and edge-deployment foundation. Their grads need almost zero ramp time on enterprise engagements with us.
Arun Joshi, Practice Director, Capgemini
We've placed 40+ RoboEdify alumni across our AI and automation teams. Strong fundamentals, sharp on the agent stack.
Sanjay Verma, Talent Director, IBM
ITOM + Predictive Intelligence is exactly the talent gap we've been struggling to close. RoboEdify is filling it for us reliably.
Anjali Desai, Practice Head, LTIMindtree
Their AI track delivers engineers who navigate data, models and integrations on customer engagements unsupervised.
Ramesh Iyer, Senior Manager, Tech Mahindra
Hired 25+ RoboEdify graduates for our AI practice. Strong coding, strong ML depth, sharp on the agent layer.
Geetha Pillai, Talent Acquisition Lead, Cyient
RoboEdify grads who blend robotics with Azure OpenAI land production-ready on day one. Rare combination, well-trained.
Priya Reddy, Talent Lead, Microsoft
AI alumni across RoboEdify
Meet alumni featured in our AI programs.
NV
Naveen Vedala
AI Agent Engineer
Hyderabad · India
Now at · TCS
TA
Tejashwini Addla
Simulation Engineer
Hyderabad · India
Now at · Deloitte
TD
Tharunesh Dillikar
Robotics Software Engineer
Seattle · United States
Now at · Accenture
MM
Mujahed Mohammed
Edge AI Engineer
Hyderabad · India
Now at · Accenture
BK
Bhargav Kumar Murala
Physical AI Engineer
Hyderabad · India
Now at · Capgemini
SL
Sai Manasa Leburi
Autonomous Systems Engineer
New York · United States
Now at · NTT Data
RD
Rahul Dhamma
Robot Learning Engineer
Hyderabad · India
Now at · Cognizant
Our locations
Come chat with us—on campus or online.
Flagship campus
Hyderabad
2nd Floor, Hitech City Road · Above Domino's · Opp. Cyber Towers, Jai Hind Enclave ·
Hyderabad, Telangana
Call
+91 8142998866
US desk
+1 256 388 7766
Opening hours
Mon–Sun · 7 AM–9 PM
Online
Global
Live online classes and mentorship, with working-professional learning options. DFT labs use the specified scan/ATPG and simulation environment, with tool access explained before enrollment.
Format
Live online + mentorship
Options
Working-professional
Learning support
Support when you need to catch up.
Freeze your seat for up to 90 days and rejoin the next class at no extra fee. TAs run catch-up sessions every Saturday, and recordings of every live session are available for the lifetime of your account.
FAQs
Questions about prerequisites, tools and completion.
Do I need to know scan or ATPG already?
No. The preparation diagnostic checks digital logic, RTL/netlists, clock/reset reasoning and scripting.
Will I use an industrial ATPG tool?
That is part of this practical-track design. The selected tool and licence access must be specified in the actual offering before you enroll.
Does MBIST mean I will test a fabricated SRAM?
The core exercise uses a behavioral memory with declared injected faults. It teaches algorithm and controller reasoning; it is not physical SRAM qualification.
Is a particular fault-coverage percentage guaranteed?
No universal percentage is promised. You report coverage for the fixed design, fault model and tool classifications, with justified exclusions.
Will I learn production ATE programming?
Production tester programming and silicon diagnosis are orientation topics rather than core ownership outcomes.
Can graduates and working engineers both join?
Yes, subject to the stated entry requirements. Both follow the same practical core, with preparation assigned through a diagnostic. Advanced pathways require the relevant foundations before their bridge.
How is the learning workload structured?
The program combines live mentor-led classes, guided labs, project work and support sessions. An advisor can explain the current class format before enrollment.
Can I study online or on campus?
RoboEdify offers its Hyderabad campus, live online classes and a working-professional format. Discuss the course-specific lab access and class format with an advisor.
What if I fall behind or need to pause?
You can freeze your seat for up to 90 days and rejoin the next class at no extra fee. Saturday catch-up sessions and recordings of every live session support your learning. Recordings remain available for the lifetime of your account.
Is placement guaranteed?
No. Career support includes portfolio and profile preparation, interview practice and role-fit introductions where available. RoboEdify does not guarantee an interview, offer, salary, employer, location or timeline.
What if I do not meet a practical requirement?
Feedback identifies the missing capability and the work needed for reassessment. Attendance alone does not meet the proposed completion standard. Confirm course-specific reassessment arrangements before enrollment.
How can I learn about fees and lab access?
Speak to a course advisor about the current offering, preparation requirements, fees, equipment or software access and learner-support terms.
Still have a question?
Find your starting point in DFT: Scan, ATPG & MBIST.
One million AI-native professionals by 2027.
Tell us about your technical background and the work you want to do. We’ll help you understand the preparation you need and how this course's projects connect to your learning goals.
Plan your learning
- Course
- Design for Testability: Scan, ATPG & MBIST
- Preparation
- Diagnostic-based preparation before the common core
- Level
- Specialist
- Curriculum
- 11 modules
Confirm your intake dates, delivery mode, fees, assessment and practical access with RoboEdify before enrolling. Course content describes the learning scope; an enquiry does not reserve a seat.